1. Field
Embodiments described herein relate generally to a nonvolatile semiconductor memory device.
2. Description of the Related Art
In the field of NAND flash memories, a stacked memory that can attain high bit density without being restricted by the limit of the resolution of the lithography technique attracts attention. For example, a nonvolatile semiconductor memory device is proposed that has a structure in which memory strings having a plurality of planar electrodes arranged at a predetermined interval in the height direction to cross columnar semiconductor films having dielectric films as charge storage layers formed to coat sides thereof are two-dimensionally arranged in a matrix shape and a planer electrode is shared by the memory strings adjacent to each other in a predetermined direction (see, for example, Japanese Patent Application Laid-Open No. 2009-267243).
Such a nonvolatile semiconductor memory device is manufactured as explained below. First, a plurality of layers of doped polysilicon films, which function as control gates, and silicon oxide films, which function as dielectric films among control gates, are alternately stacked on a semiconductor substrate on which a peripheral circuit is formed. Subsequently, a memory plug hole is formed to penetrate through a stacked film including the polysilicon films and the silicon oxide films. An ONO film is formed only on the inner wall of the memory plug hole and an amorphous silicon film is formed to fill the memory plug hole and finally crystallized, whereby the nonvolatile semiconductor memory device having the structure explained above is obtained.
In this way, in the method in the past, the columnar amorphous silicon layer has to be formed after the ONO film is formed in the memory plug hole formed in the stacked film of the polysilicon films and the silicon oxide films. Therefore, because the planar electrodes are placed among the memory strings adjacent to one another in a direction in which the electrodes are shared, it is difficult to reduce a distance between the columnar amorphous silicon layer and a columnar amorphous silicon layer adjacent thereto. In this way, there is a constraint on the arrangement of memory cells on a plane and there is a limit in a reduction of a cell area. Therefore, to increase bit density, the number of stacked memory layers has to be increased. For example, when a target of a half pitch is set to 20 nanometers, because the half pitch of about 65 nanometers to 50 nanometers is a limit of downsizing in the structure in the past, the number of stacked memory layers is equal to or larger than ten.